// `define SLAVE0    4'h0
// `define SLAVE1    4'h1
// `define SLAVE2    4'h2
// `define SLAVE3    4'h3
// `define SLAVE4    4'h4
// `define SLAVE12   4'hc
module busMartix
#(
    parameter   SLV0ENABLE = 1'b1,
                SLV0SEGLEN = 20,
                SLV0BASADR = 32'h8000_0000,
                SLV1ENABLE = 1'b1,
                SLV1SEGLEN = 20,
                SLV1BASADR = 32'h9000_0000,
                SLV2ENABLE = 1'b1,
                SLV2SEGLEN = 20,
                SLV2BASADR = 32'hA000_0000,
                SLV3ENABLE = 1'b1,
                SLV3SEGLEN = 20,
                SLV3BASADR = 32'hB000_0000,
                SLV4ENABLE = 1'b1,
                SLV4SEGLEN = 20,
                SLV4BASADR = 32'hC000_0000,
                SLV5ENABLE = 1'b1,
                SLV5SEGLEN = 20,
                SLV5BASADR = 32'hD000_0000,
                SLV6ENABLE = 1'b1,
                SLV6SEGLEN = 20,
                SLV6BASADR = 32'hE000_0000,
                SLV7ENABLE = 1'b1,
                SLV7SEGLEN = 20,
                SLV7BASADR = 32'hF000_0000
)
(
//--------------------Master signals-------------------
    input   wire    [63:00]     Master_WB_ADRo,
    input   wire                Master_WB_CYCo,
    output  reg     [63:00]     Master_WB_DATi,
    output  reg                 Master_WB_ACKi,
//------------------Slave 0 signals---------------------
    input   wire    [63:00]     Slave0_WB_DATo,
    output  wire                Slave0_WB_STBi,
    input   wire                Slave0_WB_ACKo,
//------------------Slave 1 signals---------------------
    input   wire    [63:00]     Slave1_WB_DATo,
    output  wire                Slave1_WB_STBi,
    input   wire                Slave1_WB_ACKo,
//------------------Slave 2 signals---------------------
    input   wire    [63:00]     Slave2_WB_DATo,
    output  wire                Slave2_WB_STBi,
    input   wire                Slave2_WB_ACKo,
//------------------Slave 3 signals---------------------
    input   wire    [63:00]     Slave3_WB_DATo,
    output  wire                Slave3_WB_STBi,
    input   wire                Slave3_WB_ACKo,
//------------------Slave 4 signals----------------------
    input   wire    [63:00]     Slave4_WB_DATo,
    output  wire                Slave4_WB_STBi,
    input   wire                Slave4_WB_ACKo,
//------------------Slave 5 signals---------------------
    input   wire    [63:00]     Slave5_WB_DATo,
    output  wire                Slave5_WB_STBi,
    input   wire                Slave5_WB_ACKo,
//------------------Slave 6 signals---------------------
    input   wire    [63:00]     Slave6_WB_DATo,
    output  wire                Slave6_WB_STBi,
    input   wire                Slave6_WB_ACKo,
//------------------Slave 7 signals---------------------
    input   wire    [63:00]     Slave7_WB_DATo,
    output  wire                Slave7_WB_STBi,
    input   wire                Slave7_WB_ACKo
);
//--------------------Master Data mux-------------------
    always@(*)begin
        if(Master_WB_CYCo)begin
            case(1'b1)
                Slave0_WB_STBi  : Master_WB_DATi <= Slave0_WB_DATo;
                Slave1_WB_STBi  : Master_WB_DATi <= Slave1_WB_DATo;
                Slave2_WB_STBi  : Master_WB_DATi <= Slave2_WB_DATo;
                Slave3_WB_STBi  : Master_WB_DATi <= Slave3_WB_DATo;
                Slave4_WB_STBi  : Master_WB_DATi <= Slave4_WB_DATo;
                Slave5_WB_STBi  : Master_WB_DATi <= Slave5_WB_DATo;
                Slave6_WB_STBi  : Master_WB_DATi <= Slave6_WB_DATo;
                Slave7_WB_STBi  : Master_WB_DATi <= Slave7_WB_DATo;
                default  : Master_WB_DATi <= 63'hx;
            endcase
        end
        else begin
            Master_WB_DATi <= 63'hx;    
        end
    end
//-------------------Master ACK mux-----------------------
    always@(*)begin
        case(1'b1)
            Slave0_WB_STBi  : Master_WB_ACKi <= Slave0_WB_ACKo;
            Slave1_WB_STBi  : Master_WB_ACKi <= Slave1_WB_ACKo;
            Slave2_WB_STBi  : Master_WB_ACKi <= Slave2_WB_ACKo;
            Slave3_WB_STBi  : Master_WB_ACKi <= Slave3_WB_ACKo;
            Slave4_WB_STBi  : Master_WB_ACKi <= Slave4_WB_ACKo;
            Slave5_WB_STBi  : Master_WB_ACKi <= Slave5_WB_ACKo;
            Slave6_WB_STBi  : Master_WB_ACKi <= Slave6_WB_ACKo;
            Slave7_WB_STBi  : Master_WB_ACKi <= Slave7_WB_ACKo;

            default     : Master_WB_ACKi <= 1'b0;
        endcase
    end

//-----------------Slave STB signals-----------------------
    assign Slave0_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV0SEGLEN))  ==  
                              (SLV0BASADR & (32'hffff_ffff << SLV0SEGLEN))) & SLV0ENABLE;
    assign Slave1_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV1SEGLEN))  ==  
                              (SLV1BASADR & (32'hffff_ffff << SLV1SEGLEN))) & SLV1ENABLE;
    assign Slave2_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV2SEGLEN))  ==  
                              (SLV2BASADR & (32'hffff_ffff << SLV2SEGLEN))) & SLV2ENABLE;
    assign Slave3_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV3SEGLEN))  ==  
                              (SLV3BASADR & (32'hffff_ffff << SLV3SEGLEN))) & SLV3ENABLE;
    assign Slave4_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV4SEGLEN))  ==  
                              (SLV4BASADR & (32'hffff_ffff << SLV4SEGLEN))) & SLV4ENABLE;
    assign Slave5_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV5SEGLEN))  ==  
                              (SLV5BASADR & (32'hffff_ffff << SLV5SEGLEN))) & SLV5ENABLE;
    assign Slave6_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV6SEGLEN))  ==  
                              (SLV6BASADR & (32'hffff_ffff << SLV6SEGLEN))) & SLV6ENABLE;
    assign Slave7_WB_STBi   = ((Master_WB_ADRo & (32'hffff_ffff << SLV7SEGLEN))  ==  
                              (SLV7BASADR & (32'hffff_ffff << SLV7SEGLEN))) & SLV7ENABLE;
endmodule
